Data storage in discrete locations in non conducting traps in Silicon Nitride layers or in barrier isolated potential wells in silicon nodule layers and carbon Buckyball layers, have been considered possibilities for non Volatile applications instead of the typical floating gate made of poly-silicon, for vertical scaling of the Non-Volatile Memory cells. These cells are called Location-Specific (LS) Charge storage cells as the charge is stored in discrete isolated traps or discrete potential wells in specific locations in the storage element and does not spread during operation. The problem has been mainly the erase of these cells, typically they require high voltages to be applied to the junctions and the wells to erase these types of cells as extracting charge from traps or potential wells completely is difficult. In addition high tunnel voltages will cause reverse tunneling which can cause charge to be stored. Alternate erase methods using Band to Band tunneling, where in holes generated are used to erase the electron charge, used in the mirror bit cells are making the LS storage more mainstream. But the erase limitations have prevented the LS storage structures from being used in NAND cell architecture effectively. The current discussion in the disclosure will be focused on the Nitride layer for storage element, but the Silicon nodule layer and the carbon Buckyball layer can replace the Nitride layer and operate in a similar fashion in the cells described. In the past the high voltage needs and difficulty of erase have limited the scalability of these discrete location-specific storage cells and made the poly-silicon floating gate cell the primary contender for Non-Volatile memories. As the process development has matured and technology has scaled to smaller and smaller dimensions, the poly-silicon cell has approached its scaling limitations. This has re-kindled the interest in the location-specific storage cells. In order to scale these cells it is necessary to remove the high voltage requirements that limit scaling of the memory junctions and isolation. In addition to allow NAND cell structures to be implemented using these LS elements it is necessary to have a good erase method that allow the cells to be effectively erased as a page, a block or a sector.
As explained the prior art method of erase of an NROM cell was by application of very high voltages to cause Fouler-Nordheim (FN) tunneling from and to the discrete storage locations. Due to the non-conductive nature of the storage layer and associated storage element, tunneling of carriers, typically electrons, can take place in both directions if sufficient voltage is applied across the storage element. Hence the traps can get filled by carriers moving in either direction. The FN tunneling erase in the past has relied on the location of storage in the storage element to help the erase of the cell. This has not been a very repeatable and manufacturable process and has limited the use of LS storage cells from becoming a mainstream non-volatile memory technology. The recent mirror bit technology on the other hand uses channel hot electron (CHE) generation to program using high currents and band to band tunneling at the high doped junction to supply carriers of the opposing type (holes) to neutralize the stored charge and hence erase the cell. A unique methods for moving charge into the location specific storage cells for erase is described and some possible cell structures, using this methods, are presented. The erase method proposed is the Tunnel Gun (Tun-Gun or TG) method (U.S. Pat. No. 6,479,863 B2, U.S. Pat. No. 6,384,816 B1, and U.S. Pat. No. 6,534,816 B1), which are hereby incorporated by reference, for transferring charge into the storage element or storage layer. This is a medium or voltage method, where the voltages are applied to the gate structure of the TG structure and can be implemented in a number of ways to facilitate an efficient and scalable Non-Volatile memory cell.